The present invention relates to a method for manufacturing a contact of a multi-layered metal line structure of a highly integrated semiconductor device and more particularly to a contact manufacturing method of a multi-layered metal line structure that improves step coverage by flattening the insulating layer between metal lines using spin on glass (SOG) or polyimide.
The multi-layered metal line structure is used to achieve a high integration of a semiconductor device. However, if this structure is used, a serious topology effect occurs.
The conventional method of manufacturing a contact is carried out by the following processes: SOG or polyimide layer is formed on top of the insulating layer located between the lower and upper metal lines for flattening. The etching selectivity between the SOG layer and the insulating layer located on the bottom of SOG layer is determined first and then SOG layer is etched back to a predetermined thickness for flattening (at this time, a thick SOG layer is formed over part of the lower metal line with low a topology and a thin SOG layer is formed over part with a high topology). Next, an insulating layer with a pre-determined thickness is formed on top of the flattened SOG layer. Then, several contact holes are formed by removing predetermined portions of the insulating layer on the lower metal line. At this time, since depths of contact holes are different, the lower metal line with high topology remains exposed to the etching process of the insulating layer until the lower metal line with low topology is exposed, thus damaging the surface of the metal line with high topology. Also, reliability of the semiconductor device is reduced because of a bad step coverage when the lower metal line with deep contact hole is contacted with the upper metal line.